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Introduction

  • pccx: Parallel Compute Core eXecutor
    • pccx v003 — LLM line, separate RTL repository
    • pccx vision-v001 — CNN inference track on KV260
  • Quickstart
  • Evidence
  • Roadmap

v002 Architecture

  • pccx v002 Architecture
    • Overview
    • Hardware Architecture
      • Design Rationale: v001 → v002
      • Top-Level Architecture
      • Physical Floorplan
      • Memory Hierarchy
      • KV Cache Optimization Strategy
      • GEMM Core (Systolic Array)
      • GEMV Core
      • SFU Core (Complex Vector Operations)
      • PREPROCESS Stage
      • DSP48E2 W4A8 Bit Packing and Sign Recovery
    • Instruction Set Architecture (ISA)
      • Instruction Encoding
      • Per-Instruction Encoding
      • Per-Instruction Dataflow
    • Formal Model — Sail
    • Software Stack
      • C API Overview
      • HAL — AXI-Lite MMIO Layer
    • Target Models
      • Gemma 3N E4B — Overview
      • Gemma 3N E4B — Operator-Level Pipeline
      • Gemma 3N — Attention and RoPE Constraints
      • Gemma 3N — LAuReL and PLE Calibration Modules
      • Gemma 3N — FFN Gaussian Top-K Sparsity
      • Gemma 3N E4B on pccx v002 — Execution and Scheduling
    • RTL Source Reference (v002)
      • ISA Type Package
      • NPU Top-Level
      • Compute Core Modules
      • NPU Controller Modules
      • NPU Frontend Modules
      • L2 Cache (URAM)
      • Memory Dispatch
      • Shape Constant RAM
      • PREPROCESS RTL Reference
      • Compile-Priority Packages
      • Shared Library
    • Verification
    • Vivado Build

Target Hardware

  • Devices
    • Target Hardware: Xilinx Kria KV260

pccx-lab Handbook

  • pccx-lab Handbook
    • Architecture Overview
    • CLI Reference
    • Analyzer API
    • Workflow Facade
    • pccx-lab research lineage
    • UI Panel Catalogue
    • Tauri IPC Contract
    • Verification Workflow
    • .pccx Binary Format
    • UVM Bridge
    • Cycle Loop
    • pccx-lab Quickstart
    • pccx-core Module Reference

Archive

  • Archive
    • Archive: v001 Experimental Architecture
      • pccx: Parallel Compute Core eXecutor
      • pccx ISA Specification
      • pccx ISA Spreadsheet View
      • Developer Reference for pccx v001 Host API
      • RTL Source Reference (v001)
        • Top level
        • Packages and Constants
        • NPU Controller
        • Matrix Core (GEMM)
        • Vector Core (GEMV)
        • CVO Core (SFU)
        • Memory Control
        • Preprocess
        • Library
        • Host API (C driver)

Toolchain Demos

  • Toolchain Demos
    • Mermaid — NPU block diagram
    • WaveDrom — AXI4 read transaction
    • SVG — themed 4×4 PE array
    • scienceplots — bandwidth vs batch size
    • Plot gallery
      • Batch size vs achieved HP-AXI bandwidth

Tools

  • pccx-lab — Verification Lab
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Plot gallery¶

Automatically built pages for every plots/plot_*.py script. Each script produces an IEEE-style figure via the scienceplots matplotlib style, and is rendered once per language (the scripts are shared; captions stay in English for numerics).

Follow the plotting conventions used by the existing scripts.

Batch size vs achieved HP-AXI bandwidth

Batch size vs achieved HP-AXI bandwidth

Gallery generated by Sphinx-Gallery

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Last updated on 2026-05-06
RTL Lab Docs Blog