RTL Source Reference (v002)

This section embeds key SystemVerilog modules from the pccx v002 RTL repository: pccxai/pccx-FPGA-NPU-LLM-kv260.

The RTL is cloned into codes/v002/ at CI build time. Local development requires a manual clone:

git clone https://github.com/pccxai/pccx-FPGA-NPU-LLM-kv260 codes/v002

• ISA Type Package
• NPU Top-Level
• Compute Core Modules
• NPU Controller Modules
• NPU Frontend Modules
• L2 Cache (URAM)
• Memory Dispatch
• Shape Constant RAM
• PREPROCESS RTL Reference
• Compile-Priority Packages
• Shared Library

Module status matrix (release-line v002.0)

Table 12 pccx v002 RTL module status (release-line v002.0)

Module / page	Phase status	Last verified against
ISA Type Package	landed	8c09e5e (2026-04-29)
NPU Top-Level	landed	8c09e5e (2026-04-29)
Compute Core Modules	landed	8c09e5e (2026-04-29)
NPU Controller Modules	landed	8c09e5e (2026-04-29)
NPU Frontend Modules	landed	8c09e5e (2026-04-29)
L2 Cache (URAM)	landed	8c09e5e (2026-04-29)
Memory Dispatch	landed	8c09e5e (2026-04-29)
Shape Constant RAM	in progress (Phase 3 step 1 migration)	18d4631 (2026-05-06)
PREPROCESS RTL Reference	landed	8c09e5e (2026-04-29)
Compile-Priority Packages	landed	8c09e5e (2026-04-29)
Shared Library	landed	8c09e5e (2026-04-29)

The “Last verified against” column tracks the upstream commit at which each page’s RTL excerpt and behaviour description were last reviewed. “in progress” entries are subject to change while the migration lands.